An EEPROM (Electrically Erasable and Programmable Read Only Memory) which can electrically erase stored data and further rewrite new data therein has been widely used more and more for control apparatuses or as IC cards (memory cards), because data can be erased easily in response to electric signals under the condition that the EEPROM is kept mounted or assembled on a board.
A memory cell structure as shown in FIGS. 1 to 4 has been so far known as the EEPROM suitable for a large capacity. FIG. 1 is a plan view showing a pattern of the memory cell; FIG. 2 is a cross-sectional view taken along the line A--A' in FIG. 1; FIG. 3 is a cross-sectional view taken along the line B--B' in FIG. 1; and FIG. 4 is an equivalent circuit thereof.
As depicted in these drawings, a gate oxide film 18 with a thickness of about 100 angstrom is formed on a region enclosed by a field oxide film 20 formed on a P type substrate 13. A floating gate 11 of a first poly silicon layer is formed via the gate oxide film 18. Further, a control gate 12 of a second poly silicon layer is formed on the floating gate 11 via an insulating film 19. The insulating film 19 is of three-layer structure, for instance such as O--N--O (oxide-Nitride-Oxide). The thickness of the insulating film 19 is about 200 angstrom in oxide film conversion. The control gate 12 is used as a word line of the memory cell. Further, another insulating layer 21 is formed on the control gate 12.
In addition, a source 14 and a drain 15 formed of an N+ type diffusion layer are formed on the P type substrate 13 and on both the sides of the floating gate 11 and the control gate 12. A contact hole 16 is formed open in the insulating layer 21 at such a position as to correspond to the drain 15. Further, a data line 17 of an aluminum layer is connected to the drain 15 through the contact hole 16.
The memory cell constructed as described above can realize the function corresponding to an equivalent circuit as shown in FIG. 4, in which D denotes the drain 15; S denotes the source 14; and CG denotes the control gate 12, respectively.
The operation of the memory cell thus constructed will be described hereinbelow.
To erase date, an erase voltage of 12 volts, for instance is applied to the source 14 with the drain kept floated. Further, the control gate 12 is set to 0 volts. Under these conditions, a relatively high erase voltage is applied between the floating gate 11 and the source 14 via the thin gate oxide film 18. Electrons in the floating gate 11 are emitted into the source 14 on the basis of Fowler-Nordheim tunnel effect, with the result that data is erased.
To write data, on the other hand, a voltage of about 6 volts is applied to the drain 15; a voltage of 0 volts is applied to the source 14; and a voltage of 12 volts is applied to the control gate 12. As a result, impact ionization occurs in the vicinity of the drain 15, so that electrons are injected into the floating gate 11 to write data therein.
Further, to read data, a voltage of 1 volt is applied to the drain 15; a voltage of 0 volts is applied to the source 14; and a voltage of 5 volts is applied to the control gate 12. Therefore, it is possible to obtain data "0" or data "1" on the basis of the presence or absence of electrons in the floating gate 11.
FIG. 5 shows a circuit configuration of the conventional semiconductor memory device using the memory cells constructed as described above, in which a flash type 8-bit EEPROM of byte structure is shown in particular by way of example.
In FIG. 5, the memory cells are arranged in a matrix pattern of m-rows and n-columns. The sources of these memory cells 30 are all connected in common to a terminal SS. The control gates of these memory cells 30 are connected to the row lines WL1 to WLm, respectively for each row. The drains of these memory cells 30 are connected to the column lines DL1 to DLn, respectively for each column.
Further, the terminal SS is connected to a source voltage control circuit 37, to which a high supply voltage is supplied through an external high voltage supply terminal Vpp. The row lines WL1 to WLm are connected to a row decoder 31. The column lines DL1 to DLn are connected to common junction points N-1 to N-8 via enhancement type column select transistors 33-1 to 33-n, respectively. Outputs of a column decoder 32 are applied to the gates of the column select transistors 33-1 to 33-n through column select lines CL1 to CLn, respectively.
Data writing enhancement type load transistors 34-1 to 34-8 are connected between the common junction points N-1 to N-8 and the external high voltage supply terminal Vpp, respectively. Written data Din*1 to Din*8 are inputted to written data control circuits 35-1 to 35-8 through external terminals, respectively. The inverted written data/Din*1 to/Din*8 (/D denotes an inversion signal of D) are inputted from the written data control circuits 35-1 to 35-8 to the gates of these load transistors 34-1 to 34-8, respectively.
Further, an output SW of a high voltage switching circuit 36 is supplied to the row decoder 31 and the column decoder 32. A high voltage is supplied to this switching circuit 36 through the external high supply voltage terminal Vpp.
Further, data reading sense amplifiers 38-1 to 38-8 including a load transistor, respectively are connected to the common junction points N-1 to N-8. Output circuits 39-1 to 39-8 for outputting data to the external terminals are connected to these sense amplifiers 38-1 to 38-8, respectively.
In a source voltage control circuit 37, an erase signal Erase is inputted to the gates of series-connected P type transistor 37A and N type transistor 37B, respectively. The output of the common-connected drains of these P and N type transistors 37A and 37B is inputted to the gates of series-connected P type transistor 37D and N type transistor 37E through the source and drain of an N type transistor 37C, respectively. The common-connected drains of these P and N type transistors 37D and 37E are connected to the terminal SS and also to the gate of the P type transistor 37F. The drain of the P type transistor 37F is connected to the gates of the P and N type transistors 37D and 37E, respectively. The source of the P type transistor 37A and the gate of the N type transistor 37C are connected to the supply voltage Vcc, respectively. The sources of the P type transistor 37F and the P type transistor 37D are connected to the external high supply voltage terminal Vpp.
The operation of the circuit configured as described above will be described hereinbelow.
To write data, a voltage of 12 volts is supplied to the external high supply voltage terminal Vpp. Upon application of 12 volts to the external high supply voltage terminal Vpp, the high voltage switching circuit 36 outputs 12 volts to the column decoder 32 and the row decoder 31 as the output SW, respectively. At the same time, one memory cell 30 for each output bit; that is, a sum total of 8 memory cells 30 for 8 output bits are selected on the basis of the column select lines CL1 to CLn and the row lines WL1 to WLm selected in response to address signals, respectively.
Here, the assumption is made that a voltage of 12 volts is applied to the selected line (e.g., WL1) of the row lines WL1 to WLm and another voltage of 12 volts is applied to the selected line (e.g., CL1) of the column select lines CL1 to CLn.
Here, when the written data Din*1 to Din*8 are at "0", the written data control circuits 35-1 to 35-8 (to which a high voltage is applied from the external high supply voltage terminal Vpp, respectively) output voltages of about 9 volts as the written data /Din*1 to /Din*8, respectively, so that the load transistors 34-1 to 34-8 are turned on, respectively. Accordingly, a voltage of about 6 volts is applied from the external high supply voltage terminal Vpp to the selected lines of the column lines DL1 to DLn via the load transistors 34-1 to 34-8 and the column select transistors 33-1 to 33-n, in order to write data in the corresponding memory cells 30. On the other hand, when the written data Din*1 to Din*8 are at "1", since the written data /Din*1 to /Din*8 are at "0", the load transistors 34-1 to 34-8 are all turned off, so that no voltage is applied to the drains of the selected memory cells 30 without writing data therein.
To erase data, a high voltage of about 12 volts is supplied from the external high supply voltage terminal Vpp to the terminal SS via the source voltage control circuit 37, in order to set all the column select lines CL1 to CLn and the row lines WL1 to WLm to "0" volts, so that all the memory cells are erased simultaneously.
Further, in this case, the erasure is made by applying an erase signal Erase to the source voltage control circuit 37. However, in response to the erase signal Erase, the P type transistor 37A is turned off and the N type transistor 37B is turned on. Therefore, the P type transistor 37D is turned on through the N type transistor 37C and simultaneously the N type transistor 37E is turned off, so that the external high supply voltage Vpp is outputted to the terminal SS. At the same time, the external high supply voltage Vpp is applied to the gate of the P type transistor 37F to turn off the P type transistor 37F.
Further, to read data, the data writing load transistors 34-1 to 34-8 are always tuned off, and the output SW of the high voltage switching circuit 36 is set to Vcc (5 volts). The data "1" or "0" of the memory cells 30 selected by the column decoder 32 and the row decoder 31 are sensed and amplified by the sense amplifies 38-1 to 38-8, and then outputted to the external output terminals via the output circuits 39-1 to 39-8, respectively.
As described above, in the conventional semiconductor memory device, since the external high supply voltage Vpp is applied to the device through the source voltage control circuit 37 when data are erased, the following problems arise:
FIGS. 6A to 6C are waveform diagrams for assistance in explaining the data erasure operation, in which FIG. 6A shows the waveform of a voltage outputted from the terminal SS in response to the erase signal Erase; FIG. 6B shows the tunnel current characteristics of when a bias voltage is applied to the sources of the respective transistors of the memory cells 30; and FIG. 6C shows the load characteristics of the P type transistor 37D of the source voltage control circuit 37, respectively.
As shown in FIG. 6A, when the erase signal Erase changes to "1" in the data erasure mode, the high voltage supplied from the source voltage control circuit 37 to the terminal SS rises sharply up to 12 volts. This rise time is as fast as 1 .mu.sec or less.
In the data erasure mode, a voltage of zero volts is applied to the control gates of the memory cells 30 to obtain the floating drains thereof, and further an erase voltage is applied to the sources thereof from the source voltage control circuit 37. In this case, the tunnel current I of the transistor of the memory cell 30 changes according to the source voltage Vs, as shown in FIG. 6B. In more detail, under the condition that electrons are injected into the floating gate of the memory cell 30 and the gate is kept at a negative potential, the tunnel current flows between bands on the basis of the source voltage lower by this negative voltage, as shown by the line T in FIG. 6C. At this time, when a tunnel current il ampere flows between bands, electrons are extracted from the floating gate at the intersection Q between the load line R of the P type transistor 37D and the vertical line T.
With the advance of data erasure, the potential at the floating gate rises. Therefore, the current between bands decreases gradually, so that the operating point changes from the point Q to 12 volts along the line P.
In this case, however, before the source voltage reaches 12 volts, if current flows by a cause (e.g., breakdown current) other than the leak current, there exists a problem in that the source voltage will not rise up to 12 volts and therefore the tunnel current also stops.
In other words, in the data erasure, when the source voltage of the memory cell 30 rises sharply, current between bands flows, with the result that the erasure characteristics deteriorate.
Another problem will be described hereinbelow.
As already explained, the erasure of data from the memory cell is achieved by extracting electrons existing in the floating gate 11 to the source side 14 by applying a high voltage of 12 volts to the source 14. That is, tunnel current flows due to an electric field generated between the floating gate 11 and the source 14, so that data is erased.
Therefore, there exists a problem in that the erasure characteristics differ according to dispersion in the electric field. There are various factors of causing the dispersion in the electric field, for instance such as the dispersion of the gate insulating film 18, an overlap length (as shown by X.sub.js in FIG. 3) of the floating gate 11 and the source 14, etc. Accordingly, even if a voltage is applied to the source 14 for a predetermined time, since there exist various memory cells of high electric field and memory cells of low electric field, a difference in erasure characteristics occurs between the memory cells, so that there exists a distribution in the erasure status; that is, there exist various cells of high erasure speed and low erasure speed.
FIG. 7 shown the erasure characteristics, in which the abscissa designates the voltage Vg of the control gate 12 and the ordinate designates the current Id of the drain 15. This graph shown in FIG. 7 indicates that there exists a distribution in the thresholds of the memory cells from which data are erased; that is, there exists an erasure distribution between the high erasure speed cells and the low erasure speed cells. Therefore, where the memory cell LSI is erased, if the erasure operation is kept executed until the lowest erasure speed cell can be erased, there exists a problem in that the high erasure speed cell is overerased and thereby the leak current flows under the condition that the voltage Vg of the control gate 12 is kept at 0 volts. Once the overerasure occurs, the threshold voltage of the memory cell becomes negative; the depletion occurs; the cell is turned on and the current flows even if the control gate 12 is at 0 volts, with the result that a leak current inevitably flows.
FIG. 8 is a circuit diagram for assistance in explaining the operation of the memory cell LSI in which an overerased memory cell exists. In FIG. 8, the row decoder 23 determines access to the row lines WL1 to WLm. The column decoder 22 determines access to the column lines BL1 to BLn. A number of memory cells M11 to Mn and Mm1 to Mmn are arranged in a matrix pattern in the vicinity of the intersections between the row lines WL1 to WLm and the column lines BL1 to BLn. Here, the assumption is made that the memory cell Mmn is overerased into depletion status. The data reading sense amplifier SA is connected to the column lines BL1 to BLn.
In the circuit configuration as described above, the assumption is further made that the column decoder 22 selects the column line BLn and the row decoder 23 applies a voltage of 5 V to the row line WL1 and a voltage of 0 V to the row line WLm to select the memory cell M1n in which data "0" is written. Under these conditions, no current flows through the bit line BLn. However, since a leak current I- flows through the non-selected overerased memory cell Mmn, in spite of the fact that the control gate thereof is at 0 V, the sense amplifier SA erroneously read the data in the memory cell Mln as "1". In other words, if an overerased memory cell exists along the selected column lines BL1 to BLn, a leak current flows through the overerased cell, irrespective of the fact that the overerased cell is selected or not by the row lines WL1 to WLn, with the result that the sense amplifier SA always reads "1". Namely, it is impossible to correctly read the data from the memory cells connected to the column lines BL1 to BLn on which an overerased memory cell exists.
Accordingly, it is very important to check whether the memory cells are overerased into depletion status or not, in order to secure the reliability of the operation of the memory cell LSI. In the ordinary EEPROM, it is necessary to guarantee the number of data rewriting operations beyond 10.sup.4 to 10.sup.5 times, when the memory cells are used as a memory card. After data have been rewritten repeatedly by the above-mentioned times, since electrons are trapped in the oxide film, the data rewriting characteristics deteriorate gradually. On the other hand, if the data are rewritten by the above-mentioned 10.sup.4 to 10.sup.5 times, the test time is excessively long and also meaningless. Therefore, it is very important to determine the margin in the overerasure test.
The conventional methods of testing the overerasure are disclosed in U.S. Pat. Nos. 4,841,482 or 4,860,261, respectively. In these methods, the potential of the word lines is floated about 0.5 V, for instance to get a margin of the test for checking whether the overerasure status occurs or not. In other words, the flow of the leak current is tested under the above-mentioned condition (the word line potential is floated by 0.5 V), in order to obtain a margin of 0.5 V. This is because the non-selected word lines are set to 0 V in the actual data reading operation.
However, the conventional methods involve the following problem: when the memory cell LSIs are manufactured, the threshold levels of the memory cell LSI distribute from 2 V to 3 V in the erasure operation. On the other hand, there exists a close relationship between the threshold level of the erased memory cell and the access time of the same memory cell. When the data is erased down to a lower threshold level, since a large operating current can be obtained in the data read operation, it is possible to operate the cell at a higher speed. Here, the threshold level on which data is determined to be erased is assumed to be 2.5 V, by considering that the threshold level distribution of the memory cells is about 2 V and by anticipating that the margin thereof is 0.5 V. In this case, however, the erasure threshold levels of the acutely manufactured memory cell LSI chips distribute up to about 3 V. Therefore, if an LSI having the 3 V threshold distribution is manufactured and erased at 2.5 V in the erasure test, since a leak current flows, the LSI chip becomes defective. In other words, when the erasure operation is made at a lower threshold voltage, defective chips increase and thereby the manufacturing cost increases. In contrast with this, if the erasure level is set to a higher threshold level under consideration of the high threshold distribution chips, since sufficient operating current cannot be obtained in the data reading operation, thus raising another problem in that the operation speed is low.
As described above, in the conventional semiconductor memory device, since the memory cells cannot be erased at the lower threshold level, the memory cells are not suitable for high speed operation, and further it has been difficult to improve the operation margin.
Further, FIG. 9 shows a circuit for monitoring the threshold level Vth of the conventional LSI chip. In the threshold level (Vth) measuring test mode in FIG. 9, the signal Icell is set to "1" to turn on a transistor 101 and off a transistor 102, so that a sense amplifier circuit 103 is disconnected from the bit lines of the memory cells MC, and an I/O pad 104 is connected to the bit lines BL of the memory cells MC. As described above, a voltage is applied from the I/O pad 104 to the drains of the memory cells MC, and an external supply voltage Vpp is applied to the gates thereof via a row decoder 105. Further, the potential of the selected word lines WL is changed by changing the external supply voltage Vpp.
Here, a Vpp/Vcc switching circuit 107 switches the supply voltages Vpp and Vcc, and supplies the external high supply voltage Vpp to one terminal of a P channel transistor 105A (the final stage buffer circuit) of the row decoder 105 in the data write operation and the supply voltage Vcc thereto in data read operation. Further, a transistor 108 switches the output of the vpp/Vcc switching circuit 107 and the external supply voltage Vpp or vice versa in the threshold level (Vth) measuring test mode. Here, the reason why an output of a booster circuit 109 is applied to the gate of the transistor 108 is to prevent the drain voltage applied to the memory cells MC from dropping by the threshold level Vth. In FIG. 9, the circuit includes a column decoder 110, transistors 111 selected by the column decoder 110, a memory cell array 112 and an output circuit 113.
The problems involved in the conventional circuit shown in FIG. 9 will be described hereinbelow.
Here, the assumption is made that after the threshold level distributes between 0 and V2 volts after erasure as shown in FIG. 10. At this time, the external supply voltage Vpp is changed to change the voltage applied to the gate of the memory cells MC. However, if the external supply voltage Vpp drops below the threshold level of the P channel transistor 105A of the row decoder 105, the P channel transistor 105A is turned off, so that the word line WL (l) changes to a floating status, thus it being impossible to apply a reliable voltage to the gates of the memory cells MC.
In other words, when the threshold level Vth of the P channel transistor 105A is V1, it is impossible to measure the threshold distribution of the memory cells whose threshold levels lie between 0 and V1 volts shown in FIG. 10. That is, the threshold distribution of the overerased cells cannot be measured, thus raising a serious problem in evaluation of the memory cell LSI.
As described above, in the conventional memory device, it has been difficult to erase the device so that the threshold levels of the memory cells become appropriate value, and in addition it has been impossible to measure the threshold levels appropriately.